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Flip Flop Electronic Tutorials and Circuits

# NOR Gate Flip-Flop Tutorial

Here, one input of each gate is held LOW by "pull down" resistors. The other input is cross-coupled to the output of the other gate.

Initially, as shown in diagram A, gate 2 has two LOW inputs, so its output is HIGH. This HIGH output is one input of gate 1, so the output of gate 1 is LOW. When the SET input of gate 2 is momentarily pulsed HIGH, the output of gate 2 goes LOW. This means that both inputs of gate 1 are LOW, so its output is HIGH, which is coupled to an input of gate 2.

Even though the pulse has finished, the output of gate 2 stays LOW because of this HIGH input.

The gates are now in the state shown in diagram B.

We say that the circuit has remembered or LATCHED and is in the SET state. If the SET is pulsed again, nothing happens, the circuit stays in the SET state. If the RESET on gate 1 is now pulsed HIGH, the output of gate 1 goes LOW. This is coupled to gate 2 which now has two LOW inputs, so its output goes HIGH. The gates have been RESET to their original states. If the RESET is pulsed again, nothing happens, the circuit stays in the RESET state.

Note that when one output is HIGH, the other is LOW and vice-versa.

If both inputs are taken LOW simultaneously, then there is no change; both inputs are already LOW. If both inputs are taken HIGH simultaneously, then the result is INDETERMINATE and is to be avoided.  A similar circuit can be constructed using nand gates and pull up resistors.

The inputs are pulsed low to change states.