Using the Watchdog Interrupt
In the event that the watchdog timer is not reset within the configured amount of time, the watchdog will trigger a "Watchdog Interrupt." The watchdog interrupt is a new interrupt introduced in the DS80C320.
The interrupt is enabled by setting the
EWDI bit in the new
EIE (Extended Interrupt Enable) SFR at E8h:
| SFR Bit |
Bit Label |
Bit Number |
Description |
| EIE.4 |
EWDI |
EBh |
Enable Watchdog Interrupt. When this bit is set, an interrupt through vector 63h will be triggered when WDCON.4 is set. |
When EWDI is set, a Watchdog Interrupt will be triggered when
WDCON.3 (Watchdog Interrupt Flag) is set. The Watchdog Interrupt vector is 63h.
The Watchdog Interrupt Flag (WDCON.3) is set 128 instruction cycles prior to the watchdog initiating a reboot. However, this does not necessarily mean that your interrupt routine has 128 instruction cycles available to it.
WDCON.3 is set exactly 128 instruction cycles prior to reboot, but the Watchdog Interrupt has the lowest polling interrupt priority. If another interrupt of higher priority is executing--or if another interrupt of the same priority occurs at the same instant--the other interrupt will execute first. If the other interrupt requires more than 128 instruction cycles, your Watchdog Interrupt routine will never have a chance to execute prior to reboot.
Thus, if it is critical that your application be informed of an imminent reboot, it is suggested that you give your Watchdog Interrupt a high priority and all other interrupts a low priority. You can modify the priority of the Watchdog Interrupt by modifying the corresponding bit in the new
EIP (Extended Interrupt Priority) SFR at F8h:
| SFR Bit |
Bit Label |
Bit Number |
Description |
| EIP.4 |
PWDI |
FBh |
Watchdog Interrupt Priority. When this bit is set, the watchdog interrupt is assigned high priority. When this bit is clear the watchdog interrupt is assigned low priority. |
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80C320 -
Chapter
3.3 (Watchdog
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