Instruction Address Register
(IAR) The IBM name for program counter.
The IAR can be accessed by way of a supervisor call in supervisor state, but
cannot be directly addressed in problem state.
(1995-03-21)
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Electrical and Electronics Engineers, Inc. «
Institut National de Recherche en Informatique et
Automatique «
Instruction Address Register » instruction
mnemonic » instruction prefetch » instruction
scheduling
instruction mnemonic
<programming> A word or acronym used in assembly language to represent a
binary machine instruction operation code. Different processors have different
instruction set and therefore use a different set of mnemonics to represent
them.
E.g. ADD, B (branch), BLT (branch if less than), SVC, MOVE, LDR (load register).
(1997-02-18)
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Institute of Electrical and Electronics Engineers,
Inc. « Institut National de Recherche en
Informatique et Automatique « Instruction Address
Register « instruction mnemonic » instruction
prefetch » instruction scheduling » instruction set
instruction prefetch
<architecture> A technique which attempts to minimise the time a
processor spends waiting for instructions to be fetched from memory.
Instructions following the one currently being executed are loaded into a
prefetch queue when the processor's external bus is otherwise idle. If the
processor executes a branch instruction or receives an interrupt then the queue
must be flushed and reloaded from the new address.
Instruction prefetch is often combined with pipelining in an attempt to keep the
pipeline busy.
By 1995 most processors used prefetching, e.g. Motorola 680x0, Intel 80x86.
[First processors using prefetch?]
(1998-03-29)
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Institut National de Recherche en Informatique et
Automatique « Instruction Address Register «
instruction mnemonic « instruction prefetch »
instruction scheduling » instruction set »
instruction set architecture
instruction scheduling
The compiler phase that orders instructions on a pipelined, superscalar, or VLIW
architecture so as to maximise the number of function units operating in
parallel and to minimise the time they spend waiting for each other.
Examples are filling a delay slot; interspersing floating-point instructions
with integer instructions to keep both units operating; making adjacent
instructions independent, e.g. one which writes a register and another which
reads from it; separating memory writes to avoid filling the write buffer.
Norman P. Jouppi and David W. Wall, "Available Instruction-Level Parallelism
for Superscalar and Superpipelined Processors", Proceedings of the Third
International Conference on Architectural Support for Programming Languages and
Operating Systems, pp. 272--282, 1989.
[The SPARC Architecture Manual, v8, ISBN 0-13-825001-4]
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Instruction Address Register « instruction mnemonic
« instruction prefetch « instruction scheduling
» instruction set » instruction set architecture »
Instruction Set Processor
instruction set
<architecture> The collection of machine language instructions that a
particular processor understands.
The term is almost synonymous with "instruction set architecture" since the
instructions are fairly meaningless in isolation from the registers etc. that
they manipulate.
(1999-07-05)
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instruction mnemonic « instruction prefetch «
instruction scheduling « instruction set »
instruction set architecture » Instruction Set
Processor » instrument
instruction set architecture
<architecture> (ISA) The parts of a processor's design that need to be
understood in order to write assembly language, such as the machine language
instructions and registers. Parts of the architecture that are left to the
implementation, such as number of superscalar functional units, cache size and
cycle speed, are not part of the ISA.
The definition of SPARC, for example, carefully distinguishes between an
implementation and a specification.
(1999-01-16)
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instruction prefetch « instruction scheduling «
instruction set « instruction set architecture
» Instruction Set Processor » instrument » int
Instruction Set Processor
<language> (ISP) A family of languages for describing the instruction
sets of computers.
["Computer Structures: Readings and Examples", D.P. Siewiorek et al, McGraw-Hill
1982].
(1995-10-12)
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instruction scheduling « instruction set «
instruction set architecture « Instruction Set
Processor » instrument » int » INTCODE
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