1. <networking> e-mail address.
2. <networking> Internet address.
3. <networking> MAC address.
4. <storage, programming> An unsigned integer used to select one
fundamental element of storage, usually known as a word from a computer's main
memory or other storage device. The CPU outputs addresses on its address bus
which may be connected to an address decoder, cache controller, memory
management unit, and other devices.
While from a hardware point of view an address is indeed an integer most
strongly typed programming languages disallow mixing integers and addresses, and
indeed addresses of different data types. This is a fine example for syntactic
salt: the compiler could work without it but makes writing bad programs more
ADD 1 TO COBOL GIVING COBOL « ADDD « additive «
» address bus » addressed call mode » addressee
<processor> The connections between the CPU and memory which carry the
address from/to which the CPU wishes to read or write. The number of bits of
address bus determines the maximum size of memory which the processor can
See also data bus.
ADDD « additive « address « address bus »
addressed call mode » addressee » addressing mode
addressed call mode
<communications> (ACM) A mode that permits control signals and commands
to establish and terminate calls in V.25bis.
additive « address « address bus « addressed call
» addressee » addressing mode » address mask
<communications> One to whom something is addressed. E.g. "The To, CC,
and BCC headers list the addressees of the e-mail message". Normally an
addressee will eventually be a recipient, unless there is a failure at some
point (an e-mail "bounces") or the message is redirected to a different
address « address bus « addressed call mode «
» addressing mode » address mask » address
1. <processor, programming> One of a set of methods for specifying the
operand(s) for a machine code instruction. Different processors vary greatly in
the number of addressing modes they provide. The more complex modes described
below can usually be replaced with a short sequence of instructions using only
The most common modes are "register" - the operand is stored in a specified
register; "absolute" - the operand is stored at a specified memory address; and
"immediate" - the operand is contained within the instruction.
Most processors also have indirect addressing modes, e.g. "register indirect",
"memory indirect" where the specified register or memory location does not
contain the operand but contains its address, known as the "effective address".
For an absolute addressing mode, the effective address is contained within the
Indirect addressing modes often have options for pre- or post- increment or
decrement, meaning that the register or memory location containing the effective
address is incremented or decremented by some amount (either fixed or also
specified in the instruction), either before or after the instruction is
executed. These are very useful for stacks and for accessing blocks of data.
Other variations form the effective address by adding together one or more
registers and one or more constants which may themselves be direct or indirect.
Such complex addressing modes are designed to support access to multidimensional
arrays and arrays of data structures.
The addressing mode may be "implicit" - the location of the operand is obvious
from the particular instruction. This would be the case for an instruction that
modified a particular control register in the CPU or, in a stack based processor
where operands are always on the top of the stack.
2. In IBM System 370/XA the addressing mode bit controls the size of the
effective address generated. When this bit is zero, the CPU is in the 24-bit
addressing mode, and 24 bit instruction and operand effective addresses are
generated. When this bit is one, the CPU is in the 31-bit addressing mode, and
31-bit instruction and operand effective addresses are generated.
["IBM System/370 Extended Architecture Principles of Operation", Chapter 5.,
'Address Generation', BiModal Addressing].
address bus « addressed call mode « addressee «
addressing mode » address mask » address
resolution » Address Resolution Protocol
<networking> (Or "subnet mask") A bit mask used to identify which bits in
an IP address correspond to the network address and subnet portions of the
address. This mask is often referred to as the subnet mask because the network
portion of the address can be determined by the class inherent in an IP address.
The address mask has ones in positions corresponding to the network and subnet
numbers and zeros in the host number positions.
addressed call mode « addressee « addressing mode «
address mask » address resolution » Address
Resolution Protocol » address space
<networking> Conversion of an Internet address into the corresponding
physical address (Ethernet address). This is usually done using Address
The resolver is a library routine and a set of processes which converts
hostnames into Internet addresses, though this process in not usually referred
to as resolution. See DNS.
addressee « addressing mode « address mask «
address resolution » Address Resolution Protocol
» address space » Address Strobe
Address Resolution Protocol
<networking, protocol> (ARP) A method for finding a host's Ethernet
address from its Internet address. The sender broadcasts an ARP packet
containing the Internet address of another host and waits for it (or some other
host) to send back its Ethernet address. Each host maintains a cache of address
translations to reduce delay and loading. ARP allows the Internet address to be
independent of the Ethernet address but it only works if all hosts support it.
ARP is defined in RFC 826.
The alternative for hosts that do not do ARP is constant mapping.
See also proxy ARP, reverse ARP.
addressing mode « address mask « address resolution
Address Resolution Protocol » address space »
Address Strobe » ADELE
<operating system, architecture> The range of addresses which a processor
or process can access, or at which a device can be accessed. The term may refer
to either physical address or virtual address.
The size of a processor's address space depends on the width of the processor's
address bus and address registers.
Each device, such as a memory integrated circuit, will have its own local
address space which starts at zero. This will be mapped to a range of addresses
which starts at some base address in the processor's address space.
Similarly, each process will have its own address space, which may be all or a
part of the processor's address space. In a multitasking system this may depend
on where in memory the process happens to have been loaded. For a process to be
able to run at any address it must consist of position-independent code.
Alternatively, each process may see the same local address space, with the
memory management unit mapping this to the process's own part of the processor's
address mask « address resolution « Address
Resolution Protocol « address space » Address
Strobe » ADELE » ADES
<storage> (AS) One of the input signals of a memory device, especially
semiconductor memory, which is asserted to tell the memory device that the
address inputs are valid. Upon receiving this signal the selected memory device
starts the memory access (read/write) indicated by its other inputs.
It may be driven directly by the processor or by a memory controller.
address resolution « Address Resolution Protocol «
address space « Address Strobe » ADELE » ADES
» ad hoc