8052
Microcontroller Tutorial
T2CON SFR
Author: Craig Steiner
Book:
The
8051/8052
Microcontroller:
Architecture,
Assembly
Language,
And
Hardware
Interfacing
(Paperback)
T2CON SFR
The operation of Timer 2 (T2) is controlled almost entirely by the T2CON SFR, at address C8h. Note that since this SFR is evenly divisible by 8 that it is bit-addressable.
| BIT | NAME |
BIT ADDRESS |
DESCRIPTION |
| 7 | TF2 | CFh | Timer 2 Overflow. This bit is set when T2 overflows. When T2 interrupt is enabled, this bit will cause the interrupt to be triggered. This bit will not be set if either TCLK or RCLK bits are set. |
| 6 | EXF2 | CEh | Timer 2 External Flag. Set by a reload or capture caused by a 1-0 transition on T2EX (P1.1), but only when EXEN2 is set. When T2 interrupt is enabled, this bit will cause the interrupt to be triggered. |
| 5 | RCLK | CDh | Timer 2 Receive Clock. When this bit is set, Timer 2 will be used to determine the serial port receive baud rate. When clear, Timer 1 will be used. |
| 4 | TCLK | CCh | Timer 2 Receive Clock. When this bit is set, Timer 2 will be used to determine the serial port transmit baud rate. When clear, Timer 1 will be used. |
| 3 | EXEN2 | CBh | Timer 2 External Enable. When set, a 1-0 transition on T2EX (P1.1) will cause a capture or reload to occur. |
| 2 | TR2 | CAh | Timer 2 Run. When set, timer 2 will be turned on. Otherwise, it is turned off. |
| 1 | C/T2 | C9h | Timer 2 Counter/Interval Timer. If clear, Timer 2 is an interval counter. If set, Timer 2 is incremented by 1-0 transition on T2 (P1.0). |
| 0 | CP/RL2 | C8h | Timer 2 Capture/Reload. If clear, auto reload occurs on timer 2 overflow, or T2EX 1-0 transition if EXEN2 is set. If set, a capture will occur on a 1-0 transition of T2EX if EXEN2 is set. |
Reference links to Quality Microcontroller Based Schematics and Resource